Due to advances in the fields of board interconnect technology, surface mount packaging and IC density, board level testability is becoming increasingly complex. The combination of advanced board interconnect technology, such as buried wire interconnects and double-sided boards, along with surface mount packaging creates problems for in-circuit testing of the boards. In-circuit testing, the most common board level testing method, depends upon the ability to physically probe the nodes of a circuit board. As board density (the number of ICs on a board) increases, the process of probing the board using traditional techniques becomes more difficult, due to the lack of physical access.
As the IC density (amount of logic on a chip) increases, the number of test patterns required for proper testing likewise increases. In-circuit testing relies on back-driving techniques to force input conditions to test a particular IC in a circuit. When such test is being applied to one IC on a board, neighboring ICs, whose output buffers are tied to the same nodes, may be damaged. The chance of damaging a neighboring IC increases with the length of time it takes to perform a test, which is directly related to the number of test patterns applied, and therefore, related to the IC density.
Therefore, a need has arisen in the industry to provide a test structure which provides access to particular ICs on a board, and allows testing of particular ICs without risk of damage to neighboring ICs.